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Tr i path Technol ogy, I nc. - Techni cal I nfor m ati on
TA0102A STEREO 150W (4) CLASS-T DIGITAL AUDIO AMPLIFIER DRIVER USING DIGITAL POWER PROCESSING (DPP T M ) TECHNOLOGY
Technical Information Revision 3.1 - June 2000
GENERAL DESCRIPTION The TA0102A is a 150W continuous average (4), two channel Amplifier Driver Module which uses Tripath's proprietary Digital Power Processing (DPPTM) technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
Applications
Audio/Video Amplifiers/Receivers Pro-audio Amplifiers Automobile Power Amplifiers Subwoofer Amplifiers
Benefits
Reduced system cost with smaller/less expensive power supply and heat sink Signal fidelity equal to high quality ClassAB amplifiers High dynamic range compatible with digital media such as CD and DVD
Features
Class-T architecture Proprietary Digital Power Processing technology Supports wide range of output power levels
"Audiophile" Quality Sound 0.05% THD+N @ 20W, 8 0.03% IHF-IM @ 30W, 8 80W @ 8, 0.1% THD+N, VS = +/-45V 150W @ 4, 0.1% THD+N, VS = +/-45V High Power 100W @ 8, 1% THD+N, VS = +/-45V 170W @ 4, 1% THD+N, VS = +/-45V High Efficiency 90% @ 85W @ 8, VS = +/-33.75V 88% @ 155W @ 4, VS = +/-33.75V Dynamic Range = 108 dB Requires only N-Channel MOSFET output transistors High power supply rejection ratio Mute input Outputs short circuit protected Over- and under-voltage protection Bridgeable, single-ended outputs 38-pin quad package Supports 100kHz BW of Super Audio CD and DVD-Audio (refer to Application Note for specifics)
Typical Performance
THD+N versus Output Power
10 5
20Hz - 22kHz BW f = 1kHz BBM = 25nS Vs = +/-45V Av = 14.8 ST STP19NB20 MOSFET
2
1
THD+N (%)
0.5
0.2
RL = 8
0.1 0.05
RL = 4
0.02 0.01 1 2 5 10 20 50 100 200
Output Power (W)
1
TA102A -Rev.3.1/06.01
Tripath Technology, Inc. - Technical Information
Absolute Maximum Ratings
SYMBOL VS V5 VN12 TSTORE TA Positive 5V Bias Supply Supply Voltage: Nominal +12V referenced to VSNEG Storage Temperature Range Operating Free-air Temperature Range PARAMETER Supply Voltage (VSPOS & VSNEG) VALUE +/-70 6 18 -40 to 150 -20 to +80 UNITS V V V C C
Notes:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Damage will occur to the device if VN12 is not supplied or falls below the recommended operating voltage when VS is within its recommended operating range.
Operating Conditions MIN.
SYMBOL VS V5 VN12
PARAMETER Supply Voltage (V spos & V sneg) Positive 5V Bias Supply
TYP. 5 12
MAX. +/-49 5.5 13.2
UNITS V V V
+/-28 4.5 10.8
Supply Voltage: Nominal +12V referenced to V SNEG
Note: Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits.
Electrical Characteristics
Unless otherwise specified, TA = 25C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL Iq Quiescent Current (no load, BBM0=BBM1=0) PARAMETER +33.75V -33.75V +5V VN12 MIN. TYP. 25 30 45 110 5.1 5.2 42 46 +/-28 +/-49 3.5 1 0.315 4 18 0.475 3.5 1 0.63 0.70 77 500 0.77 2 5 25 2 MAX. 75 50 65 160 UNITS mA mA mA mA A A mA mA V V V V mA mA mA mA V V V V/V mV
IS I5 IVN12 VU VO V IH - MUTE V IL - MUTE IDDMUTE
Source Current @ POUT = 150W, 4 +33.75V -33.75V Source Current for 5V Bias Supply @ POUT = 150W, RL = 4 Source Current for VN12 Supply @ POUT = 150W, RL = 4 Under Voltage (V spos & V sneg) Over Voltage (V spos & V sneg) High-level Input Voltage (MUTE) Low -level Input Voltage (MUTE) Mute Supply Current (no load, 145nS delay) +33.75V -33.75V +5V VN12 High-level Output Voltage (HMUTE & OVERLOADB)
V OH V OL V TOC AV Voffset
Low -level Output Voltage (HMUTE & OVERLOADB) Over Current Sense Voltage Threshold Gain Ratio V O/V I, RIN = 0 Offset Voltage, no load, MUTE = Logic low (before nulling)
Minimum and maximum limits are guaranteed but may not be 100% tested.
2
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Performance Characteristics - Single Ended, Vs = +45V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL POUT PARAMETER Output Pow er (Continuous Average/Channel) CONDITIONS THD+N = 0.1% RL = 8 RL = 4 THD+N = 1% RL = 8 RL = 4 PO = 20W/Channel, RL = 8 MIN. TYP. 80 130 100 170 0.05 0.05 98.5 85 67 82 300 MAX. UNITS W W W W % % dB dB dB % V
THD + N IHF-IM SNR CS PSRR eNOUT
Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Pow er Supply Rejection Ratio Pow er Efficiency Output Noise Voltage
19kHz, 20kHz, 1:1 (IHF), RL = 4 POUT = 30W/Channel A-Weighted, POUT = 88W/Ch, RL = 8 0dBr = 30W, RL= 8 f = 120Hz, Vripple = 100 mV POUT = 230W/Channel, RL = 4 A-Weighted, no signal, input shorted, DC offset nulled to zero
Performance Characteristics - Single Ended, Vs = +33.75V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL POUT PARAMETER Output Pow er (Continuous Average/Channel) CONDITIONS THD+N = 0.1% RL = 8 RL = 4 THD+N = 1% RL = 8 RL = 4 PO = 20W/Channel, RL = 8 MIN. TYP. 47 77 65 110 0.05 0.03 100 85 67 90 195 MAX. UNITS W W W W % % dB dB dB % V
THD + N IHF-IM SNR CS PSRR eNOUT
Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Pow er Supply Rejection Ratio Pow er Efficiency Output Noise Voltage
19kHz, 20kHz, 1:1 (IHF), RL = 4 POUT = 30W/Channel A-Weighted, POUT = 47W/Ch, RL = 8 0dBr = 20W, RL= 8 f = 120Hz, Vripple = 100 mV POUT = 85W/Channel, RL = 8 A-Weighted, no signal, input shorted, DC offset nulled to zero
Minimum and maximum limits are guaranteed but may not be 100% tested.
Notes:
1. 2. V5 = +5V, VN12 = +12V referenced to VSNEG Test/Application Circuit Values: D = MUR120T3 diodes, RIN = 22.1K RD = 33RS = 0.025RG = 30 ROCR1 = ROCR2 = 0, LF = 18uH (Amidon core T200-2) CF = 0.22uF, CD = 0.1uF, CIN = 1uF, CBY = 0.1uF Power Output MOSFET, M = ST STP19NB20 BBM0 =BBM1 = 1
3
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Pin Description
Pin 1 2 3 4 5, 6 7, 8 9, 12 10, 11 13, 14 15, 16 17, 30 18, 29 19 20, 27 21, 26 22, 25 23 24 28 31, 32 33, 34 35 36, 37, 38 Function AGND OVERLOADB V5 MUTE IN2, IN1 BBM0, BBM1 GNDKELVIN1, GNDKELVIN2 OCR2, OCR1 OCS1L+, OCS1LOCS1H-, OCS1H+ LO1COM, LO2COM FDBKN1;FDBKN2 VN12 LO1, LO2 HO1COM, HO2COM HO1, HO2 VSPOS VSNEG PGND OCS2L-, OCS2L+ OCS2H-, OCS2H+ HMUTE NC Description Analog Ground Logic output. When low, indicates that the level of the input signal has overloaded the amplifier. Positive 5 Volts Logic input. When high, both amplifiers are muted. When low (grounded), both amplifiers are fully operational. Single-ended input (Channel 1 & 2) Break-before-make timing control Kelvin connection to speaker ground (Channel 1 & 2) Over-current threshold adjustment (Channel 1 & 2) Over Current Sense resistor, Channel 1 low-side Over Current Sense resistor, Channel 1 high-side Kelvin connection to source of low-side transistor (Channel 1 & 2) Feedback (Channel 1 & 2) Voltage: +12 V from VSNEG. Refer to Application Information section. Low side gate drive output (Channel 1 & 2) Kelvin connection to source of high-side transistor (Channel 1 & 2) High side gate drive output (Channel 1 & 2) Positive supply voltage Negative supply voltage Power Ground Over Current Sense resistor, Channel 2 low-side Over Current Sense resistor, Channel 2 high-side Logic output. When high, indicates that the output stages of both amplifiers are shut off and muted. Not Connected - Must Be Left Floating
38
37
36
35
34
33
32
31
30
29
28
OCS2H+
1
LO2COM
FDBKN2
OCS2L+
OCS2H-
OCS2L-
HMUTE
PGND
NC
NC
NC
AGND OVERLOADB
LO2
27
2
HO2COM
26
3
V5
HO2 VSNEG VSPOS
25
4
MUTE
24
5
IN2 IN1 BBM0 GND KELVIN1 BBM1 GND KELVIN2
23 22 21 20
6 7 8
HO1 H01COM LO1 VN12 19
OCS1H+
LO1COM
9
10
11
12
13
14
15
16
17
38 PIN QUAD MODULE PIN OUT
TOP VIEW
FIGURE 1
4
FDBKN1 18
OCS1L+
OCR2
OCR1
OCS1H-
OCS1L-
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
TEST/APPLICATION CIRCUIT
TA0102A
18 FDBKN1 16 OCS1H+ RS 15 OCS1HM 22 CIN RIN V5 10K 1M 0.1 uF 1M 4 IN1 6 HO1 RG M 20 LO1 RG LF D CBY CF RD CD RL D CBY
.1uF 100uF
VSPOS
Processing & Modulation
21 HO1COM
13 OCS1L+ 17 LO1COM MUTE 14 OCS1L-
RS VSNEG
.1uF 100uF
9 GNDKELVIN1 OCR1 ROCR1 OCR2 ROCR2 BBM0 BBM1 7 RS 8 33 OCS2HM 25 CIN RIN V5 10K 1M 0.1 uF 1M NC NC NC V5 0.1 uF 36 37 38 3 AGnd 1 PGnd 28 IN2 5 HO2 RG M 27 LO2 RG LF D CBY CF RD CD RL D CBY
.1uF 100uF
11 10
2 35
OVERLOADB HMUTE
29 FDBKN2 34 OCS2H+ VSPOS
Processing & Modulation
26 HO2COM
32 OCS2L+ 30 LO2COM 31 OCS2L-
RS VSNEG
.1uF 100uF
12 GNDKELVIN2 23 24 19 VSPOS VSNEG VN12
NC - Not Connected (Must Be Left Floating) Note - Heavy Lines Indicate High-Current Paths
Figure 2
5
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Typical Performance at Vs = +45V
THD+N versus Output Power
10 5
20Hz - 22kHz BW f = 1kHz BBM = 25nS Vs = +/-45V Av = 14.8 ST STP19NB20 MOSFET
Efficiency versus Output Power
90 80 70
RL = 4
2
1
Efficiency (%)
THD+N (%)
60 50 40 30 20 10
22Hz - 22kHz BW f = 1kHz BBM = 145nS VS = +/-45V Av = 20.75 ST STP19NB20 MOSFET
0.5
0.2
RL = 8
0.1 0.05
RL = 4
0.02 0.01 1 2 5 10 20 50 100 200
0 0
Output Power (W)
50
100
150
200
250
Output Power (W)
Intermodulation Performance RL = 4
10Hz - 80kHz BW BBM = 25nS VS = +/-45V Av = 14.8
THD+N versus Frequency RL = 4
10 20Hz - 22kHz BW 5 BBM = 25nS Pout = 30W/Channel 2 V = +/-45V S 1 Av = 14.8 0.5 ST STP19NB20 MOSFET
+10 +0 19kHz, 20kHz, 1:1 -10 Pout = 30W/Channel -20 0dBr = 11Vrms
THD+N (%)
0.2 0.1 0.05 0.02 0.01
FFT (dBr)
-30 ST STP19NB20 MOSFET -40 -50 -60 -70 -80 -90
0.005 0.002 0.001 10 20 50 100 200 500 1k 2k 5k 10k 20k
-100
60
100
200
500
1k
2k
5k
10k
20k 30k
Frequency (Hz)
Frequency (Hz)
Channel Separation versus Frequency
+0 -10
RL = 4
20Hz - 22kHz BW BBM = 25nS Pout = 30W/Channel VS = +/-45V Av = 14.8 ST STP19NB20 MOSFET
+0 -10 -20 -30 -40
A-Weighted Noise FFT
20Hz - 22kHz BW BBM = 25nS Pout = 0 VS = +/-45V RL = 4 Av = 14.8 ST STP19NB20 MOSFET
Channel Separation (dBr)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20
Noise (dBv)
-50 -60 -70 -80 -90 -100 -110 -120 -130 -140
20
50
100
200
500
1k
2k
5k
10k
20k
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
6
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Typical Performance at Vs = +33.75V
THD+N versus Output Power
10 5
Efficiency versus Output Power
100 90 80 RL = 8
2
20Hz - 22kHz BW f = 1kHz BBM = 25nS VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET 8 4
1 0.5
Efficiency (%)
THD+N (%)
70 60 50 40 30 20 10 RL = 4
0.2 0.1
0.05
0.02 0.01
22Hz - 22kHz BW f = 1kHz BBM = 145nS VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET
0 25 50 75 100 125 150 175
0
1 2 5 10 20 50 100 200
Output Power (W)
Output Power (W)
THD+N versus Frequency versus Bandwidth, RL = 8
10 5
THD+N versus Frequency versus Bandwidth, RL = 4
10 5
BBM = 25nS Pout = 20W/Channel VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET
BBM = 25nS Pout = 30W/Channel VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET
2 1
2 1
THD+N (%)
THD+N (%)
0.5
0.5
0.2 0.1 0.05
0.2 0.1 0.05
30kHz BW
30kHz BW
0.02 0.01
22kHz BW
0.02 0.01
22kHz BW
10
20
50
100
200
500
1k
2k
5k
10k
20k
10
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
THD+N versus Frequency versus Break Before Make, RL = 8
10 5
THD+N versus Frequency versus Break Before Make, RL = 4
10 5
20Hz - 22kHz BW Pout = 20W/Channel VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET
20Hz - 22kHz BW Pout = 30W/Channel VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET
2 1
2 1
THD+N (%)
0.5
THD+N (%)
0.5
145nS
0.2
0.2 0.1
145nS
105nS 65nS
105nS
0.1
65nS
0.05
0.05
25nS
0.02 0.01 10
0.02 0.01
25nS
20
50
100
200
500
1k
2k
5k
10k
20k
10
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
7
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Typical Performance
THD+N versus Output Power versus Supply Voltage RL = 8
20Hz - 22kHz BW f = 1kHz BBM = 25nS Av = 14.8 ST STP19NB20 MOSFET
10
10
THD+N versus Output Power versus Supply Voltage RL = 4
20Hz - 22kHz BW f = 1kHz BBM = 25nS Av = 14.8 ST STP19NB20 MOSFET
THD+N (%)
THD+N (%)
1
1
27V
0.1
33.75V
50V
27V
33.75V
50V
0.1
0.01 1 10
Output Power (W)
100
1000
0.01 1 10
Output Power (W)
100
1000
+10 +0 -10 -20
Intermodulation Performance RL = 8
10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 25nS Pout = 20W/Channel VS = +/-33.75V 0dBr = 13Vrms Av = 14.8 ST STP19NB20 MOSFET
+10 +0 -10 -20 -30
Intermodulation Performance RL = 4
10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 25nS Pout = 30W/Channel VS = +/-33.75V 0dBr = 11Vrms Av = 14.8 ST STP19NB20 MOSFET
FFT (dBr)
FFT (dBr)
-30 -40 -50 -60 -70 -80 -90 -100
-40 -50 -60 -70 -80 -90 -100
60
100
200
500
1k
2k
5k
10k
20k 30k
60
100
200
500
1k
2k
5k
10k
20k 30k
Frequency (Hz)
Frequency (Hz)
Channel Separation versus Frequency
A-Weighted Noise FFT
+0 -10 -20 -30 -40 -50
Channel Separation (dBr)
20Hz - 22kHz BW BBM = 25nS Pout = 0 VS = +/-33.75V RL = 4 Av = 14.8 ST STP19NB20 MOSFET
+0 -10 -20 -30 -40 -50 -60 -70 -80
20Hz - 22kHz BW BBM = 25nS Pout = 30W/Channel @ 4 Pout = 20W/Channel @ 8 VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET
Noise (dBv)
-60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k
4
8 -90 -100 20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
8
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Functional Description
TA0102A Amplifier Operation Figure 3 is a simplified diagram of one channel (channel 1) of a TA0102A amplifier to assist in understanding its operation.
TA0102A
18 FDBKN1 16 OCS1H+ VSPOS RS 15 OCS1HVBOOT
Over-current Detection
M RG M RL RG
MUTE RIN CIN BBM0 BBM1 IN1
4 6 7 8
22 HO1
Processing & Modulation
21 HO1COM 19 VN12 20 LO1 17 LO1COM
Low-pass Filter
OCR1 ROCR1
11
Over-current 13 OCS1L+ Detection
14 OCS1L9 GNDKELVIN1 2 35 OVERLOADB HMUTE VSPOS VSNEG
RS VSNEG
Over/Under Voltage
V5 3 A Gnd 1 P Gnd 28
23 24
Figure 3. Simplified TA0102A Amplifier The audio input signal (IN1) is fed into the processor internal to the TA0102A, where a modulation pattern is generated. This pattern is spread spectrum and varies between approximately 200kHz and 1.5MHz. Complementary copies of the switching pattern are level-shifted by the MOSFET drivers and output from the TA0102A where they drive the gates (HO1 and LO1) of external power MOSFETs that are connected as a half bridge. The output of the half bridge is a power-amplified version of the switching pattern that switches between VSPOS and VSNEG. This signal is then low-pass filtered to obtain amplified audio.
9
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
The processor portion of the TA0102A is operated from a 5-volt supply (between V5 and AGND). In the generation of the complementary modulation pattern for the output MOSFETs, the processor inserts a "break-before-make" dead time between when it turns one transistor off and it turns the other one on in order to minimize shoot-through currents in the MOSFETs. The dead time can be programmed by setting the break-before-make control bits, BBM0 and BBM1. Feedback information from the output of the half-bridge is supplied to the processor via FDBKN1. Additional feedback information to account for ground bounce is supplied via GNDKELVIN1. The MOSFET drivers in the TA0102A are operated from voltages obtained from VN12 and LO1COM for the low-side driver, and VBOOT (generated internal to the TA0102A) and HO1COM for the highside. Only N-Channel MOSFETs are required for both the top and bottom of the half bridge. VN12 must be a stable 12V above VSNEG. The gate resistors, RG, are used to control MOSFET slew rate and thereby minimize voltage overshoots. Over- and Under-Voltage Protection The TA0102A senses the power rails through VSPOS and VSNEG for over- and under-voltage conditions. The over- and under-voltage limits are Vo and Vu respectively as specified in the Electrical Characteristics table. If the supply voltage exceeds Vo or drops below Vu, the TA0102A shuts off the output stages of the amplifiers and asserts a logic level high on HMUTE. The removal of the over-voltage or under-voltage condition returns the TA0102A to normal operation and returns HMUTE to a logic level low. Please note that the limits specified in the Electrical Characteristics table are at 25C and these limits may change over temperature. Over-current Protection The TA0102A has over-current protection circuitry to protect itself and the output transistors from short-circuit conditions. The TA0102A uses the voltage across a resistor, RS (measured via OCS1H+, OCS1H-, OCS1L+ and OCS1L-), that is in series with each output MOSFET to detect an over-current condition. RS and ROCR are used to set the over-current threshold. The OCS pins must be Kelvin connected for proper operation. See "Circuit Board Layout" in Applications Information for details. An over-current condition will cause the TA0102A to shut off the output stages of the amplifiers and supply a logic level high on HMUTE. The occurrence of an over-current condition is latched in the TA0102A and can be cleared by toggling the MUTE input or cycling power. Overload When logic low, the OVERLOADB pin indicates that the level of the input signal has overloaded the amplifier and that the audio output signal is starting to distort. The OVERLOADB signal is active only when an overload is present. The OVERLOADB signal can be used to control a distortion indicator light or LED through a simple buffer circuit. Mute When a logic high signal is supplied to MUTE, both amplifier channels are muted (both high- and low-side transistors are turned off) and a logic level high is output on the HMUTE pin. When a logic level low is supplied to MUTE, both amplifiers are fully operational and a logic level low is supplied on HMUTE. There is a delay of approximately 200 milliseconds between the de-assertion of MUTE and the un-muting of the TA0102A.
10
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Application Information
Amplifier Gain and Input Resistor Selection The value of the input resistor, RIN, is based on the required voltage gain, AV, of the amplifier according to: AV = 387 x103/(RIN + 5000) where RIN = Input resistor value in ohms. Input Capacitor Selection CIN can be calculated once a value for RIN has been determined. CIN and RIN determine the input low-frequency pole. Typically this pole is set at 10Hz. CIN is calculated according to: CIN = 1/((2 x fP)(RIN + 5000)) where: RIN = Input resistor value in ohms. fP = Input low frequency pole (typically 10Hz). DC Offset Adjust While the DC offset voltages that appear at the speaker terminals of a TA0102A amplifier are typically small, Tripath recommends that any offsets during operation be nulled out of the amplifier with a circuit like the one shown connected to IN1 and IN2 in the Test/Application Circuit. Nulling should be performed with the inputs shorted to ground. It should be noted that even after nulling, the DC voltage on the output of a TA0102A amplifier with no load in mute mode is approximately 2.5V. This offset does not need to be nulled. The output impedance of the amplifier in mute mode is approximately 10 KOhms. This means that the 2.5V drops to essentially zero when a typical load is connected. Supply Voltage and Output Power The relationship between the bipolar power supply voltage needed, VS, for a given RMS output power, POUT, into a given load, RL, at a given level of THD (total harmonic distortion) is approximated by: VS = (2 x RL x POUT) 0.5/(K x RL/(RL + RON + RS + RCOIL)) where: RON = The at-temperature RDSON of the output transistors, M. RCOIL = Resistance of the output filter inductor. RS = Sense Resistor K = THD Factor, a number fixed by the algorithms in the TA0102A's signal processor that provides the relationship between THD at full output power of the amplifier and VS. K corresponds to THD at full output power as follows: THD 0.1% 1% 10% K 0.83 0.95 1.09
Typical measurement graphs of POUT versus supply voltage for various levels of THD are also included in this data sheet to help determine the supply voltage.
11
TA0102A, Rev. 3.1/06.01
Tripath Technology, Inc. - Technical Information
Bridged Operation Note that the two channels of a TA0102A amplifier can be used to provide a single, bridged amplifier of almost four times the output power of one of the single-ended amplifier channels. To configure a bridged amplifier, the input to one TA0102A channel must be the inverted signal of the input to the other channel. Low-frequency Power Supply Pumping A potentially troublesome phenomenon in single-ended switching amplifiers is power supply pumping. This is caused by current from the output filter inductor flowing into the power supply output filter capacitors in the opposite direction as a DC load would drain current from them. Under certain conditions (usually low-frequency input signals), this current can cause the supply voltage to "pump" (increase in magnitude) and eventually cause over-voltage/under-voltage shut down. Moreover, since over/under-voltage are not "latched" shutdowns, the effect would be an amplifier that oscillates between on and off states. If a DC offset on the order of 0.3V is allowed to develop on the output of the amplifier (see "DC Offset Adjust"), the supplies can be boosted to the point where the amplifier's over-voltage protection triggers. One solution to the pumping issue is to use large power supply capacitors to absorb the pumped supply current without significant voltage boost. The low frequency pole used at the input to the driver determines the value of the supply capacitor required. This works for AC signals only. Another solution to the supply pumping problem uses the fact that music has low frequency information that is correlated in both channels (it is in phase). This information can be used to eliminate boost by putting the two channels of a TA0102A amplifier out of phase with each other. This works because each channel is pumping out of phase with the other, and the net effect is a cancellation of pumping currents. The phase of the audio signals needs to be corrected by connecting one of the speakers in the opposite polarity as the other channel.
CONTACT INFORMATION
World Wide Sales Offices
United States & Europe SE Asia & China Japan & Korea
Jim Hauer Eugene Hsu Osamu Ito
jhauer@tripath.com ehsu@tripath.com ito@tripath.com
408.567.3089 886.2.2653.7428 81.42.334.2433
TRIPATH TECHNOLOGY, INC
3900 Freedom Circle Santa Clara CA 95054
408.567.3000
www.tripath.com
12
TA0102A, Rev. 3.1/06.01

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